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74HC590 device highlight

Introduction
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. Unlike unregistered counters, this device produces glitch-free outputs by virtue of its storage register. The 74HC590 is also available in the space saving DQFN 14 package (2.5mm x 3.5mm x 0.85mm).
Uses
Uses include binary counters, remote control holding registers, and signal synchronization architectures in LCD TVs.
In audio/video applications, due to differences in layout paths, the digital video and audio signals may need to be synchronized to avoid the audience seeing lip movement without hearing any speech. The circuit above uses the 74HC590 counter to program a delay. Signal is only applied to the SIGin input of the ASIC after the counter has reached a predetermined count. The 74HC590 counts the number of CLK pulses (or SYNC pulses) as determined by the design, which is set by connecting the parallel outputs to the 3-input AND gate. In the example above, outputs Q0, Q3, and Q5 are used to set the count to 42 CLK cycles (25 + 23 + 20 + 1 cycle). Once the count is reached, the output of the latch becomes high and Signal is applied to SIGin.
Features
  • 8-bit storage register
  • Master reset
  • Independent counter and register clocks
  • Wide supply range of 2.0V to 6.0v
  • -40°C to +125°C operation
  • Available in SO, TSSOP, and DQFN packages
Products

Block Diagram

The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage.

74HC590 Binary Counter

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Samples

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